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| 9db1200c idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 1414f ?06/30/10 twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm datasheet 1 general description output features the ics9db1200 is an intel db1200 differential buffer specification device. this buffer provides 12 differential clocks at frequencies ranging from 100mhz to 400 mhz. the ics9db1200 is driven by a differential output from a ck410b+ or ck509b main clock generator. ? 12 - 0.7v current-mode differential output pairs. ? supports zero delay buffer mode and fanout mode. ? bandwidth programming available. ? 100-400 mhz operation in pll mode ? 33-400 mhz operation in bypass mode functional block diagram key specifications ? output cycle-cycle jitter < 50ps. ? output to output skew: 50ps ? phase jitter: pcie gen2 < 3.1ps rms ? phase jitter: qpi < 0.5ps rms ? 64-pin tssop package ? available in rohs compliant packaging features/benefits ? 3 selectable smbus addresses for easy system expansion ? spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread ? supports undriven differential outputs in power down mode for power management. description db1200 rev 2.0 intel yellow cover device src_in src_in# dif(11:0)) control logic bypass#/pll smbdat smbclk vttpwrgd#/pd spread compatible pll 12 iref oe_(11:0)# 12 fs(2:0) high_bw# m u x adr_sel
idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 2 1414f ?06/30/10 pin configuration vdd 1 64 vdda dif_in 2 63 agnd dif_in# 3 62 iref gnd 4 61 fs0 oe0# 5 60 oe11# dif_0 6 59 dif_11 dif_0# 7 58 dif_11# vdd 8 57 vdd gnd 9 56 gnd oe1# 10 55 oe10# dif_111 54dif_10 dif_1# 12 53 dif_10# oe2# 13 52 oe9# dif_214 51dif_9 dif_2# 15 50 dif_9# gnd 16 49 gnd vdd 17 48 vdd oe3# 18 47 oe8# dif_319 46dif_8 dif_3# 20 45 dif_8# oe4# 21 44 oe7# dif_422 43dif_7 dif_4# 23 42 dif_7# vdd 24 41 vdd gnd 25 40 gnd oe5# 26 39 oe6# dif_527 38dif_6 dif_5# 28 37 dif_6# **adr_sel29 36vttpwrgd#/pd high_bw# 30 35 bypass#/pll fs231 34fs1 smbclk 32 33 smbdat 64-tssop ** indicates 120k ohm pulldown 9db1200c smbus address selection (pin 29) adr_sel voltage smbus adr (wr/rd) low <0.8v dc/dd mid 1.2 idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 3 1414f ?06/30/10 pin description pin # pin name type description 1 vdd pwr power supply, nominal 3.3v 2 dif_in in 0.7 v differential true input 3 dif_in# in 0.7 v differential complementary input 4 gnd pwr ground pin. 5oe0# in active low input for enabling dif pair 0. 1 =disable outputs, 0 = enable outputs 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complementary clock output 8 vdd pwr power supply, nominal 3.3v 9 gnd pwr ground pin. 10 oe1# in active low input for enabling dif pair 1. 1 =disable outputs, 0 = enable outputs 11 dif_1 out 0.7v differential true clock output 12 dif_1# out 0.7v differential complementary clock output 13 oe2# in active low input for enabling dif pair 2. 1 =disable outputs, 0 = enable outputs 14 dif_2 out 0.7v differential true clock output 15 dif_2# out 0.7v differential complementary clock output 16 gnd pwr ground pin. 17 vdd pwr power supply, nominal 3.3v 18 oe3# in active low input for enabling dif pair 3. 1 =disable outputs, 0 = enable outputs 19 dif_3 out 0.7v differential true clock output 20 dif_3# out 0.7v differential complementary clock output 21 oe4# in active low input for enabling dif pair 4 1 =disable outputs, 0 = enable outputs 22 dif_4 out 0.7v differential true clock output 23 dif_4# out 0.7v differential complementary clock output 24 vdd pwr power supply, nominal 3.3v 25 gnd pwr ground pin. 26 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 27 dif_5 out 0.7v differential true clock output 28 dif_5# out 0.7v differential complementary clock output 29 **adr_sel in this tri-level input selects one of 3 smbus addresses. see the smbus address select table for the addresses. 30 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 31 fs2 in frequency select pin. 32 smbclk in clock pin of smbus circuitry, 5v tolerant idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 4 1414f ?06/30/10 pin description pin # pin name type description 33 smbdat i/o data pin of smbus circuitry, 5v tolerant 34 fs1 in 3.3v frequency select latched input pin. 35 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 36 vttpwrgd#/pd in vttpwrgd# is an active low input used to sample latched inputs and allow the device to power up. pd is an asynchronous active high input pin used to put the device into a low power state. the internal clocks and plls are stopped. 37 dif_6# out 0.7v differential complement clock output 38 dif_6 out 0.7v differential true clock output 39 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 40 gnd pwr ground pin. 41 vdd pwr power supply, nominal 3.3v 42 dif_7# out 0.7v differential complement clock output 43 dif_7 out 0.7v differential true clock output 44 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 45 dif_8# out 0.7v differential complement clock output 46 dif_8 out 0.7v differential true clock output 47 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 48 vdd pwr power supply, nominal 3.3v 49 gnd pwr ground pin. 50 dif_9# out 0.7v differential complement clock output 51 dif_9 out 0.7v differential true clock output 52 oe9# in active low input for enabling dif pair 9. 1 = tri-state outputs, 0 = enable outputs 53 dif_10# out 0.7v differential complement clock output 54 dif_10 out 0.7v differential true clock output 55 oe10# in active low input for enabling dif pair 10. 1 = tri-state outputs, 0 = enable outputs 56 gnd pwr ground pin. 57 vdd pwr power supply, nominal 3.3v 58 dif_11# out 0.7v differential complement clock output 59 dif_11 out 0.7v differential true clock output 60 oe11# in active low input for enabling dif pair 11. 1 = tri-state outputs, 0 = enable outputs 61 fs0 in 3.3v frequency select latched input pin. 62 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 63 agnd pwr analog ground pin for core pll 64 vdda pwr 3.3v power for the pll core. idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 5 1414f ?06/30/10 absolute max electrical characteristics - input/supply/common output parameters symbol parameter min max units vdda 3.3v core supply voltage 4.6 v vdd 3.3v logic supply voltage 4.6 v v il input low voltage gnd-0.5 v v ih input high voltage v dd +0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v t a = 0 - 70c; supply voltage v d d = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% gnd - 0.3 0.8 v 1 input high current i ih v in = v d d -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 operating supply current i dd3. 3op full active, c l = full load; 375 ma 1 powerdown current i dd3. 3p d all differential pairs tri-stated 24 ma 1 f ipll pll mode 100 400 mhz 1 f ibypass bypass mode 33 400 mhz 1 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 peakin g when high_bw#=0 1.5 2 db 1 peakin g when high_bw#=1 1.5 2 db 1 pll bandwidth when high_bw#=0 2 3 4 mhz 1 pll bandwidth when high_bw#=1 0.7 1 1.4 mhz 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 modulation frequency f mod triangular modulation 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 12 cycles 1,3 tdrive_pd t drvpd dif output enable after pd de-assertion 300 us 1,3 tfall t f fall time of oe# 5 ns 1 trise t r rise time of oe# 5 ns 1 1 guaranteed by design and characterization, not 100% tested in production. 2 see timin g dia g rams for timin g requirements. 3 time from deassertion until out p uts are >200 mv capacitance input low current pll bandwidth bw input frequency pll jitter peaking j peak idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 6 1414f ?06/30/10 electrical characteristics - clock input parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdi f differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing min centered around differential zero electrical characteristics - dif 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , r ref =475 ? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max volta g evovs 1150 1 min volta g evuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossin g volta g e ( var ) d-vcross variation of crossin g over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values 0 pp m1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t pdbyp bypass mode, v t = 50% 2.5 4.5 ps 1 t pdpll pll mode v t = 50% -250 250 ps 1 skew, output to output t sk3 v t = 50% 50 ps 1 pll mode 50 p s1,5 bypass mode as additive j itte r 50 p s1,5 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 3 i ref = v dd /(3xr r ). for r r = 475 idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 7 1414f ?06/30/10 electrical characteristics - phase jitter parameter symbol conditions min typ. max units notes pcie gen 1 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=10 ns , ftrk=1.5 mhz ) 35 86 ps 1,2,3 pcie gen 2 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=12 ns) lo-band content ( 10khz to 1.5mhz ) 1.1 3 ps rms 1,2 pcie gen 2 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=12 ns) hi-band content ( 1.5mhz to n yq uist ) 2.3 3.1 ps rms 1,2 qpi s p ecs refclk p hase j itte r 0.25 0.5 p s rms 2,4 notes on phase jitter: 2 device driven b y 932s421bglf or e q uivalent 3 ber of 1e-9 4 measured at 133mhz usin g csi_133_mhz_6_4bg_12ui tem p late in intel su pp lied clock jitter tool. tjphase jitter, phase 1 see http://www.pcisig.com for complete specs. guaranteed by design and characterization, not tested in production. idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 8 1414f ?06/30/10 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9 1414f ?06/30/10 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 10 1414f ?06/30/10 general smbus serial interface information for the 9db1200c how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address dc (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address dd (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack note: addresses show assumes pin 29 is low. idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 11 1414f ?06/30/10 smbus table: frequency select register pin # name control function t yp e0 1 pwd bit 7 high_bw# high or low bw rw high bw low bw latch bit 6 bypass#/pll b y pass (non-pll mode) or pll mode rw b y pass pll latch bit 5 reserved reserved rw x bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 fs2 frequenc y select 2 rw latch bit 1 fs1 frequency select 1 rw latch bit 0 fs0 frequency select 0 rw latch smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 dif_7 output control (disable = hi-z) rw disable enable 1 bit 6 dif_6 output control (disable = hi-z) rw disable enable 1 bit 5 dif_5 output control (disable = hi-z) rw disable enable 1 bit 4 dif_4 output control (disable = hi-z) rw disable enable 1 bit 3 dif_3 output control (disable = hi-z) rw disable enable 1 bit 2 dif_2 output control (disable = hi-z) rw disable enable 1 bit 1 dif_1 output control (disable = hi-z) rw disable enable 1 bit 0 dif_0 output control (disable = hi-z) rw disable enable 1 smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 dif_11 output control (disable = hi-z) rw disable enable 1 bit 2 dif_10 output control (disable = hi-z) rw disable enable 1 bit 1 dif_9 output control (disable = hi-z) rw disable enable 1 bit 0 dif_8 output control (disable = hi-z) rw disable enable 1 smbus table: output enable readback pin # name control function t yp e0 1 pwd bit 7 oe7# oe# pin readback r enabled disabled x bit 6 oe6# oe# pin readback r enabled disabled x bit 5 oe5# oe# pin readback r enabled disabled x bit 4 oe4# oe# pin readback r enabled disabled x bit 3 oe3# oe# pin readback r enabled disabled x bit 2 oe2# oe# pin readback r enabled disabled x bit 1 oe1# oe# pin readback r enabled disabled x bit 0 oe0# oe# pin readback r enabled disabled x - - reserved b y te 0 - - reserved - - - reserved - see fs table b y te 1 43,42 38,37 27,28 22,23 19,20 14,15 11,12 6,7 b y te 2 - - - - 58,59 53,54 38,37 50,51 45,46 b y te 3 43,42 27,28 22,23 19,20 14,15 11,12 reserved reserved reserved reserved 6,7 idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 12 1414f ?06/30/10 smbus table: output enable readback pin # name control function t yp e0 1 pwd bit 7 reserved reserved r 0 bit 6 reserved reserved r 0 bit 5 reserved reserved r 0 bit 4 reserved reserved r 0 bit 3 oe11# output control (disable = hi-z) r enabled disabled x bit 2 oe10# output control (disable = hi-z) r enabled disabled x bit 1 oe9# output control (disable = hi-z) r enabled disabled x bit 0 oe8# output control (disable = hi-z) r enabled disabled x note: for an output to be enabled, both the output enable bit and the oe# pin must be enabled. this means that the output enable bit must be '1' and the corresponding oe# pin must be '0'. smbus table: vendor & revision id register pin # name control function t yp e0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e0 1 pwd bit 7 rw 1 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 smbus table: byte count register pin # name control function t yp e0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 reserved 58,59 53,54 b y te 4 - device id 1 device id 6 device id 7 (msb) device id is c0 hex device id 5 device id 4 device id 3 device id 0 device id 2 b y te 7 - writing to this register configures how many bytes will be read back. - - - - - - - b y te 6 - - - - - - - - - vendor id - - - - revision id - - - b y te 5 50,51 45,46 - - reserved reserved - reserved idt ? twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 13 1414f ?06/30/10 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 ordering information part / order number shipping packaging package temperature 9DB1200CGLF tubes 64-pin tssop 0 to +70c 9DB1200CGLFt tape and reel 64-pin tssop 0 to +70c ?lf? after the package code denotes the pb-free configuration, rohs compliant. 9db1200c twelve output differential buffer for pcie gen1/gen2, qpi, and fbdimm 14 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date description page # a 12/18/2007 1. updated smbus serial interface information. 2. release to final. 10 b 4/7/2008 added input clock parameters 6 c 8/28/2008 1. updated phase jitter numbers 2. added pll bw and jitter peaking specs 3. added input to output delay specs 5. updated stab ilization time to 1.8ms from 1.0ms d 9/15/2009 1. corrected pin number references in smbus bytes 1 and 3 2. added typical values to phase jitter table. various e 11/4/2009 changed clk stabilization spec from 1.0 to 1.8 ms 5 f 7/1/2010 corrected power groups table for input clock, 2 |
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